1. Field of the Invention
The present invention relates generally to the design of digital logic devices. More specifically, the present invention relates to the design of digital logic devices, which include on-chip memory, to facilitate debugging and testing of such devices. Still, more particularly, the invention relates to an on-chip logic analyzer, which operates in conjunction with a portion of on-chip cache memory to support on-chip storage of debug and performance data.
2. Background of the Invention
The design and development of digital logic circuits has become increasingly complex, due in large measure to the ever-increasing functionality offered in such circuits. Integrated circuits are constantly surpassing milestones in performance, as more and more functionality is packaged into smaller sizes. This enhanced functionality requires that a greater number of transistors be included in an integrated circuit, which in turn requires more rigorous testing to insure reliability once the device is released. Thus, integrated circuit designs are repeatedly tested and debugged during the development phase to minimize the number and severity of errors that may subsequently arise. In addition, chips may be tested to determine the performance characteristics of the device, including the speed or throughput of the chip, software running on the chip, or the aggregate performance of the system.
As integrated circuits become more complex, the length of the debug phase increases, requiring a greater advanced lead-time before product release. In addition, as the complexity of integrated circuits increase, it becomes necessary to fabricate more prototype iterations of the silicon (or “spins” of silicon) in order to remove successive layers of bugs from the design, thereby increasing the engineering and materials cost of the released product. It would be desirable to reduce these engineering and material costs and speed up the product cycle. Moreover, if more data, or more accurate data was available for analysis, the designers and debuggers might be able to expedite the design and debug process for the product, thereby minimizing the number of spins and the time to release the product.
One of the chief difficulties encountered during the debug phase of a product is identifying the source of an error. This can be extremely difficult because the error may make it impossible to obtain state information from the integrated circuit. For example, in a processor, an error may cause the processor to quit executing, thus making it impossible to obtain the state data necessary to identify the source of the error. As a result, the debug process requires that the debug team infer the source of the error by looking at memory accesses by the processor or patterns of activity on other external busses. The normal technique for probing external busses is to solder a wire onto a terminal or trace. Unfortunately, merely adding a soldered wire to a terminal or trace can create signal reflections, which may distort the data being monitored. Thus, the manual probing of bus terminals and traces is impractical and inaccurate, especially those attached to high speed, highly complex chips. More sophisticated techniques are also used, but are expensive and suffer, albeit to a lesser degree, from the same effects. Further, because the state information available on these busses is typically a small subset of the processor's state, the debug team must make guesses regarding the state of data internal to the processor. If the internal state of the processor could be acquired and stored, these inferences would be replaced by solid data. By reducing the designer's uncertainty and increasing the available data, this would be beneficial in solving problems with the processor hardware or software.
In certain products under development, such as new microprocessors under development by the assignee of the present invention, the number of transistors is exceedingly large and their dimensions are exceedingly small. Both of these factors make it practically impossible to probe internal terminals of the chip or internal wire traces. Moreover, to the extent that certain internal terminals and traces could be probed, the conventional methods for conducting such a probing operation are extremely expensive, and some might potentially corrupt the state of the terminals and traces being probed. Consequently, the only common technique currently available to test or probe the state of terminals and traces in highly complex chips is to route signals through the chip's external output terminals, to some external interface. This approach, however, suffers in several respects.
First, as noted above, the signals obtained from the external output terminals are removed from the signal states of the internal terminals and traces. Thus, this technique requires the debugging team to infer the state of the internal terminals and traces from signals appearing on an external bus. Second, routing the desired state to external terminals often requires more wiring, silicon, drivers, pads and power than is affordable. Attempts to do so can compromise the normal functioning of the chip. And costs escalate throughout the design, often impacting the micropackaging and system board as well as the die. Third, oftentimes the internal clock rate of the chip operates at a much higher rate than the external logic analyzers that receive and process the data. As an example, processor designs currently under development operate at clock speeds up to and exceeding 2.0 GHz. The fastest commercial logic analyzers, despite their expense, are incapable of operating at GHz frequencies. Thus, either certain data must be ignored, or some other mechanism must be employed to capture the high-speed data being generated on the chip. The typical approach is to run the chip at a slower clock speed so the data can be captured by external test equipment. This solution, however, makes it more difficult to detect the bugs and errors that occur when the chip is running at full clock speeds. Some errors that occur at full clock speed will not be detected when the clock speed is reduced to accommodate the off-chip logic analyzers. Also, increasingly the processor connects to external components that have a minimum speed, below which they will not operate. These speeds require the processor to operate faster than the external logic analyzer can accommodate.
As an alternative to sending data off-chip, attempts have been made to capture certain state data on chip, thereby reducing the problems of interfacing slower speed test equipment with high-speed devices. In this approach, history buffers, and even on-chip logic analyzers (OCLA) are provided to acquire and store event and/or time sequenced data on the chip itself. In the past, to the extent that designers sought to incorporate memory onto the chip for debug and test purposes, dedicated memory devices (usually RAM) were used. Thus, in prior art designs that attempted to capture debug and test information on-chip, a dedicated memory structure was incorporated into the chip design solely to store data for the debug and test modes. The problem with this approach, however, is that it requires the allocation of a significant amount of chip space to incorporate such dedicated memory devices, and these memory devices, while used extensively during the design and development phase of the chip, add little or nothing to the performance of the chip once it is released into production. Thus, the inclusion of dedicated memory space on the chip represents an opportunity cost, and means that functionality and/or performance is sacrificed to include this dedicated memory on the chip. Consequently, the inclusion of memory for debug purposes, while helpful in the debug and test phase, is generally viewed as undesirable because of the accompanying loss of performance and functionality that must be sacrificed. If a dedicated memory device is included on the chip, system designers normally require that such a memory be very small in size to minimize the cost increase (silicon cost is an exponential function of area, and memories are large structures), as well as the performance and functionality loss that accompanies the inclusion of such a dedicated memory. As the size of the dedicated memory becomes smaller, so too does the prospect that the state information stored in the dedicated memory will be sufficient to assist in the debug process. Thus, as the dedicated memory space becomes smaller, so too does the probability that useful debug data will be captured. In relative terms, the largest dedicated on-chip memories typically are incapable of storing very much data.
It would be desirable if a system or technique was developed that would permit the capture of more debug information to reduce cycle times, and the costs associated with designing and debugging a chip. It would also be desirable if the system was capable of acquiring data at the internal clock rate, and was capable of storing the data for subsequent retrieval and analysis. It would further be beneficial if sufficient quantities of test and debug data could be stored to increase the probability that meaningful data regarding bugs was captured. Further, it would be advantageous if the processor or chip was debuggable and diagnosable in the field, as well as in the laboratory. In particular, it would be advantageous if other problems, including errors in executing software application programs, could be detected and solved using the debug system. Such a system would permit customers and programmers to resolve software conflicts and to optimize system performance. Also, it would be desirable if the memory did not add cost to the processor and if its presence did not detract from the features or performance of the processor, at least in normal operation. Despite the apparent advantages that such a system would offer, to date no such system has been developed.